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Altera_Forum's avatar
Altera_Forum
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21 years ago

Interface to User Logic and DMA...

Hi All, I've got a situation where the IUL and/or DMA components don't fit well. My chip (a USB controller) requires substancially different timing for Read and Write. Additionall...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hi Mike,

Thanks. I'm not very handy with creating my own external logic. I can do very simple things with the graphical editor and I can write simple VHDL.

Anyway, I look in the .ptf and you're right there are separate Read_Wait_States and Write_Wait_States. I think I'll edit the IUL to use clocks instead of ns and play with these

two values.

I guess I could also edit the dma.v file to insert the recovery time perhaps. (Maybe with the HW Engineer&#39;s help http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif )

Any additional ideas or insights appreciated. I&#39;ll post my findings.

Thanks,

Ken