Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Interacting with NIOS II Processor

Hi there, If a Nios II processor needs to control the rest of FPGA logic through a set of registers and also monitor the status through another set of registers, what is the preferrable way of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Also, I got the impression that the avalon interface will handle the clock domain boundary automatically. Is it true for the following scenario?

Let's say all the registers will be used in a different clock domain (clk1) from the avalon mm master interface (i.e. Nios II core, on clk0 domain), is it ok for me to associate my avalon mm slave with clk1 domain and use those registers in clk1 domain trouble free?

Thanks,

Hua