instruction master address range only 256Mbyte ?

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originally posted by niosiiuser@Feb 20 2006, 08:40 AM

hello michael,

if bit 31 of the address is set the data cache won’t be used during this access. so if you read from 0x80000000 you will get the data from 0x00000000 (not 0x80000000) directly.

regards,

niosiiuser

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Hello niosIIuser,

so my information about bit 31 of the addressline was correct. Access to any data above 0x80000000 will not delive data from the cache. we still have the datacache problem with ldwio delivering old data even with q51sp1 & nios51sp1

But what i do not understand is the end of your posting. why does a read from 0x80000000 deliver data from 0x00000000 ???

And how can i do the address setup inside sopc without the 256MByte boundary ? i want to have the datacache for sdram, flash etc but not for my ip-modules. if i setup one of my ip modules to have its starting address at 0x80000000 i cannot re-generate the design as the button is greyed out.

Regards

Michael Schmitt