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Altera_Forum's avatar
Altera_Forum
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11 years ago

iniche memory access between hardware and nios cpu

New here and am having a problem with the iniche stack and the simple socket server. When I see a new tcp session initiated to the simple socket server, i write off the contents of that first packet (the syn) to a memory location which maps to a cpu memory location. I can happily read out the contents that I have written, but there is a massive disconnect if I write back to that memory location in the soft cpu. the hardware side does not see the update, it just reads back what it originally put there.

I believe I have the wires connected properly, but I am not clear if there is another step that i am missing to facilitate what I am trying to do.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Your problem description is very consistent with not having taken appropriate precautions with the processor data cache.

    Does your NIOS include data cache? Is your software taking any precautions to make sure your written data is leaving the cache?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Your problem description is very consistent with not having taken appropriate precautions with the processor data cache.

    Does your NIOS include data cache? Is your software taking any precautions to make sure your written data is leaving the cache?

    --- Quote End ---

    pardon my naivety, but how do i disable the data cache? or even know if the nios is including it? this is my first project leveraging the nios cpu.

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The settings can be modified by in the Qsys system. You can access the settings wizard in an existing Qsys system by double-clicking on the instance in Qsys. In a new system, you have access to the wizard when you instantiate the component.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You probably need to use the data cache for normal program accesses to memory - otherwise it will be slower than slow.

    Initially just use uncached accesses to the frame buffer area (if you aren't using the mmu, the easiest way to acomplish this is to set the high bit on the addresses).

    However you'll probably need to use the data cache flush and invalidate functions/instructions to give reasonable performance when accessing the buffers.