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sirujjan's avatar
sirujjan
Icon for New Contributor rankNew Contributor
1 year ago

Infinite looping in NIOS-II Eclipse alt_irq.h

Good day gentlemen I am facing problem related to either the NIOS-II Eclipse processing or DDR2 SDRAM memory interfacing in platform designer. I am using DE-4 board which have two on-board DDR2 SO-...
Nios Cpu
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,

Can you try to separate the PLL reference clock source for both DDR2?

  • Maybe you can provide DDR2_1 PLL reference clock source from OSC_50_B3 (PIN_AV22).
  • And DDR2_2 PLL reference clock source from OSC_50_B4 (PIN_AV19).

Regards,

Adzim