http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ph34r.gif Well - as with many other people from what I&#39;ve read - I get the old verify failure message when trying to download any project including just a hello_world program: Downloading 00000020 ( 0%) Downloading 00010000 (71%) Downloaded 91KB in 1.1s (82.7KB/s) Verifying 00000020 ( 0%) Verify failed between address 0x20 and 0xFFFF Leaving target processor paused HOW CAN I GET RID OF THIS ERROR - OR CAN I JUST NEVER RUN PROGRAMS AGAIN? thanks,

Hi Lemonoje, THere are so many reasons for the Verify fail, that is why it is so popular. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif Here are a few that I have seen 1. Bad memory interface, physical board problem 2. Timing issue with memory 3. Lack of non-volatile memory. This confuses processor. Hope that helps a little. -Baycool

Hi Lemonojo, are you sure you downloaded the right NIOS II into your board... Cheers, Danny

Well, the memory interface is a straight SDRAM instantiated in SOPC and then all the signals are routed to the chip. The memory in terms of timing works fine because I tested it using LabVIEW making calls to FS2&#39;s MDI to perform adderss/data bus tests, etc... Everything works doing basic R/W peek/pokes from the FS2 CLI. Thanks for the feedback. Any other ideas? PS - I am also getting Verify Failed from the Nios II flash programmer (from the sdk shell) when trying to load flash. I even tried re-installing Nios II 5.1 - no luck.

If you have problems with downloading programs from the IDE, I suggest to try reconfigure your FPGA with a "simple" test design that is a sub-set of your design. For example to isolate if your problem is SDRAM or SRAM, try to use/add onchip_memory to run hello world from. If the onchip_memory program runs, but loading the program to SDRAM/sram still fails, I would take a closer look at the memory timing or phase setting. Once feature I&#39;ve found useful in sorting out a "verify failure" is to have a System ID peripheral (this is found in the SOPC Builder "other" components group) in my system design. This will sort out if I accidentally loaded the wrong system on my development board or if the board gets reset into a "safe" design on a NIOS II dev board. When I download a program to a board, if I have the wrong system loaded it will flag a different time stamp. Another useful part of this is if the system ID tag is something odd like FFFF_FFFF, it shows that I could have a hardware issue like: 1) some setting error in my design that is messed up my system like I forgot to set "unused IOs to tri-state" (by default Quartus II will set all unused IOs to drive ground which may cause issues with other componets on the board that are not expecting the FPGA to pull its pins to ground). 2) line noise and my JTAG port needs a pull-up resistor/cap on a signal to handle line noise or I could have a bad USB-blaster etc.... Good luck in isolating the problem

I also use the system ID feature to make sure I have the correct hardware. That&#39;s a great idea to make some internal RAM to try and run out of. The problem with that may be that the Stratix II (2S15) doesn&#39;t have much RAM in it at all (even compared to the lowest Stratix I). I know a hello_world project barely fit into my one Stratix I internal RAM design, and like I said it has much more RAM. Nonetheless, I&#39;ll try it. I am also trying to look at the JTAG signals to see if something looks bad there...

Infamous Verify Failed | Altera Community

22 Replies

Altera_Forum
Honored Contributor
19 years ago
--- Quote Start ---
originally posted by bigpunx@Nov 13 2006, 08:20 AM
i am trying to load the uclinux image for the de2 board. i've loaded the sof and pof and downloaded using the wiki instructions. i keep getting the following message..

downloading 630kb in 7.7s
verfying 00500000 <0%>
verify failed between address 0x500000 and 0x502a19

anybody know why i can't get this working? i'm using the de2_net project and zimage_de2_net files. it should work but for me it doesn't. please help me make this de2 board more than a 500$ paper weight that blinks.
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The sdram address range of de2 is 0-0x00800000.
The zImage will be loaded to 0x00500000.
SO it loaded, but verify failed.

Do you use quartus2 v6.0 sp1, nios2 v6.0 sp1, de2 system disc v1.3 ?

Do you use quaruts2 to config the de2 with DE2_NET.sof before nios2-download?
The config data of fpga will lose when power off.

Have you tried some demo programs from sdram?
Altera_Forum
Honored Contributor
19 years ago
--- Quote Start ---
originally posted by crisjory@Feb 3 2006, 09:57 AM
i found it!!

i was using a c0 output pll for the sdram_clk, and sometimes it dont achieve the desired phase shift for the sdram. now i m using a e0 output pll, it is exclusive for external output pll and dont receive influence from internal routing.
i hope this can help another guys....
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Hello, I am getting the old veriy failed error message. However, I am using the cycloneII Device and i don't think cycloneII supports the E0 output pll. I was wondering what device you were using.

Thank you

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Infamous Verify Failed

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