Infamous Verify Failed

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originally posted by crisjory@Feb 3 2006, 09:57 AM

i found it!!

i was using a c0 output pll for the sdram_clk, and sometimes it dont achieve the desired phase shift for the sdram. now i m using a e0 output pll, it is exclusive for external output pll and dont receive influence from internal routing.

i hope this can help another guys....

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Hello, I am getting the old veriy failed error message. However, I am using the cycloneII Device and i don&#39;t think cycloneII supports the E0 output pll. I was wondering what device you were using.

Thank you