Honored Contributor
Honored ContributorHey bigboss25,
Thanks for your input. I, too, have been burned with using async signals in an synchronous (FPGA) design. As a matter of fact, early in this project's design, I re-used some simple, "known working" code, and it behaved erratically. After an evening of thought I realized I was being thumped on the nose by this "async signal in a synchrous land" problem. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif The key players in my present problem are: 1)NiosII processor, 2)ASIC chip, 3)VHDL code consisting of a pipelined calculation (multipliers, adders) and 4)VHDL state machine sequencing/feeding data from ASIC to the calculator. The# 1 Nios and# 4 FSM both must talk to# 2 ASIC although never at the same time. The Nios "engages" the hardware calculation mode and sequencer and does not intervene until it wants to stop the flow of data. My problem is that the ASIC is behaving oddly. It appears that it is getting errant initialization data. I'm in the process of trying to add timing constraints to the compilation to see if that improves things. In reference to your suggestions, the Nios and the FSM are synchronous with no async signals involved, at least no obvious ones. There is certainly the possibility that I've glanced over one/some. The power of the abstraction that VHDL gives the designer is wonderful and it is very very easy to forget good engineering practices. I certainly don't miss doing Karnaugh maps; however, a working knowledge of the "old school" rules (e.g., async/sync) is still important. Still scratching my head. I'll keep everyone posted. thanks for posting! steve --- Quote Start --- originally posted by bigboss25@Mar 24 2006, 06:48 AM hello,
i fear that your problem is due to some asynchronous signal in your design. so your behaviour is very fitting dependant ( a fit may work fine while a second fit without changing any line code may crash !).
i experimented such erratic phenomena a few year ago (when i started fpga design).
some things i learned (golden rules now for me) :
1) always make your design full synchronous . it is not always possible but in 99% it is !
2) ensure that you treated metastability on asynchronous input signals.
hope this will help you.
http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/wink.gif
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