Inconsistent HW behavior

Hello,

I fear that your problem is due to some asynchronous signal in your design. So your behaviour is very fitting dependant ( a fit may work fine while a second fit without changing any line code may crash !).

I experimented such erratic phenomena a few year ago (when i started FPGA design).

Some things I learned (golden rules now for me) :

1) always make your design full synchronous . It is not always possible but in 99% it IS !

2) ensure that you treated metastability on asynchronous input signals.

Hope this will help you.

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

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originally posted by sulrich@Mar 22 2006, 01:12 PM

hello,

i&#39;m seeing odd/inconsistent behavior in my system that i&#39;m developing. operations (hardware and software) that were working on the board stop working when unrelated vhdl code is changed and recompiled.

the board is a custom board with a cyclone 1c20, a custom asic, and various usb and interface ics. i am using the niosii processor and c-code to develop some calculation/ algorithms for the system. due to speed and throughput requirements, the calculations must eventually reside in hardware. once i determine the algorithm, i migrate the calculations to a hardware-based module in vhdl using some altera megawizard lpms and some custom vhdl code. the new module is then integrated into the main vhdl.

specifically, my problem is that as i tweaked the algorithm&#39;s vhdl (invert a signal, register another, etc.) i started seeing weird behavior in the rest of my system. for example, the nios processor initializes other chips on the board (interface, asic). functions, chips, etc. that were functioning beforehand stop working. most of these functions are not related to the vhdl code being developed. i have found that i can comment out a line of c-code or change another line in the vhdl and some functions will start functioning again.f

This problem is maddening and has halted development. Has anyone seen this behavior before? [/b]

I have seen something vaguely similar on a previous product several years ago using an Altera 20K100 part and strictly VHDL code (no NIOS). I resolved the problem by loading the design into Altera OEM versions of Leonardo Spectrum and FPGA Express which evidently had better error checking routines within the compiler. Once the syntax errors were identified (not seen in Quartus), I made the changes to the design and recompiled the design in Quartus and everything worked as designed.

I recently upgraded to Q5.1, SOPC, and IDE (and had using Q5.0 seeing the same problem)and have been seeing inconsistent behavior in my system.

I would seek help from Altera Support and may eventually do that; however, without a specific indentifiable and reproducable problem that is not specific to my hardware, I doubt if they would be able to help.

Any suggestions greatly appreciated.

thanks.

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[/b]

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