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15 years agoI use quartus 9.1 sp2 and nios 10.0 (i also try nios 9.1).
I have made a more simple project with only an epcs controller, a sram controller, +sysid, jtag uart and a pio for debug purpose. I was using the locked signal from an alt_pll to reset the Nios. It was asserted several ms before fpga conf_done signal was asserted so now I use an external reset signal. But it still doesn't work, Nios doesn't boot. When I program the epcs16 with a jic file (composed by hw & sw), only the hardware boots. After hardware has booted from flash, I can flash the software with Nios IDE, it boots correctly (no more verifying problem...). If I assert (briefly) the external reset signal, the Nios is reseted but never reboots. I both try reset_vector in sram and in flash. I don't understand why the Nios doesn't reboot, especially when the reset vector is in sram ?? Is it because Nios has been downloaded by jtag/ide ? It works as if the reset_vector always point to a bad memory region...