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Altera_Forum
Honored Contributor
12 years agoYes,Nios requires at least one avalon interface to communicate with my design. So i added few Avalon slave signals (which i don't need but its required for Avalon interface between Nios and My design) such as read_en,write_en,read,write,address. The HDL component file generated now has the signals that are present in my design which i have exported using the conduit interface. Then i instantiated this HDL component file in a top module and passed the Clk and reset signals. And yes thanks for the tip i used the same reset generated by system. The system works as expected.
Thank you.