Implementing interrupt based PIO read for NIOS II

You might want to consider using a 2nd nios cpu as a 'soft dma' engine.

This could run in a tight loop copying data to shared memory from where the other cpu sends in to the host.

This moves the tight realtime processing to somewhere where no other code is active.

You probably need less than 4kB each code and data (don't call into libc at all), share the data with your other cpu, and the code with whatever loads it. Export the nios reset signals to some control entity.

I'm doing something similar in order to run sixty four 64kb full duplex hdlc channels. In my case the host interface is PCIe - so neither cpu needs any OS software. The linker script initialises sp and gp and then jumps to into the C.