I want Nios 200MHz , SDRAM 100MHz. How to?

Also keep in mind if you plan on placing your code in that same SDRAM by running them on different clock domains you are going to add a lot of read latency due to the clock crossing. Depending on your cache size and the way your algorithms are coded this may lead to less performance than if everything was on the same domain. People usually create half-rate bridges to handle this assuming the two clocks are in phase.