I need some help of creating shared ddr sdram memory

Dear BadOmen,

Thanks for your explanation.

I think it makes no sense to have a cacheable shared memory between processors,right?

So if I understand correctly, I only have the following 3 choices:

1. Remove the data cache;

2.Use tight coupled memory;

3. Use regular on chip memory or other memory(e.g., SDRAM,SRAM) and use nono-cacheable instructions(like IOWR/IORD or remap the memory as uncacheable as you said)

Am I right? Then I think I will see how much resource do I have and choose between choice 2 and choice 3 :)