I need some help of creating shared ddr sdram memory

Hi, BadOmen,

Exactly. Originally I used the mailbox core to do the on-chip shared memory communication. I think the mailbox is kind of like the FIFO as you said. Howerver , it is very slow. The speed is about one tens of the Ethernet communication!( I am not sure whether I have done something wrong). So now I am thinking using the shared memory and hardware mutex core.

On-chip memory is a limited resources. I am thinking whether I can use the ddrsdram or the sram to build the shared memory. So you mean if I use the regular on-chip memory connecting to the regullar master port of the processor, it will not bypass the cache.Rihgt?