I need some help of creating shared ddr sdram memory

Tightly coupled memory is a regular on-chip memory configured to be 32-bit wide, read latency of 1, and connected to only a single tightly coupled master. This gives a deterministic access time of 0 cycles for writes and 1 cycle for reads.

Other memories in your system might be multi-mastered or accessed by the cache both of which will cause non-deterministic access times. The nice thing about using tightly coupled memory for shared memory is that a) it's the fastest memory you can use b) accesses to it bypass the cache. So you could dual port an on-chip memory, connect a tightly coupled data master from each CPU to it, and use some sort of algorithm/hardware to prevent data hazards. You could use the mutex hardware component for example to make sure both CPUs don't attempt to access the same memory.

I on the other hand prefer to use FIFOs to move data between processor cores since the data hazards are not a problem that way. This method doesn't scale when you have a lot of processors that need to communicate with each other since you have to use a lot of FIFOs to do that. I recommend you get your software up and running first and if you need more speed then determine if other shared data mechanisms may be needed.