hw multiplier for Cyclone

Nios II, release 1.0, doesn't support hardware multiply on Cyclone.

We have received many requests for this so expect to see it in a future release.

As for the divide custom instruction, Nios II/f has optional support for a built-in divide instruction

that the compiler will use if the option is enabled. This replaces the divide custom instruction for Nios II.

Also, we found a couple of corner-case bugs with the divide custom instruction so decided to turn it off.

The corner cases are when you divide 0x0/0x80000000 or 0x80000000/0x80000000 you get the wrong result.

I got the tip to select a device with hw-multiblier-blocks (i.e. Cyclone-II) in the SoPC-Builder, generate the processor and prior to compile in Quartus change an option in the ???_mult_cell.vhd file - has someone done this successfully to get a working hw-multiplier for a Cyclone device?

Fast multiplication (and division) is very important for us because we use the Cyclone with Nios in a hard realtime system for high dynamic industrial motion control.

James:

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As for the divide custom instruction, Nios II/f has optional support for a built-in divide instruction

that the compiler will use if the option is enabled. This replaces the divide custom instruction for Nios II.[/b]

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Where can I find this option?

Thank you for your help

Chris

I don&#39;t know if Cyclone II would have it in the GUI but it shows up as a check box under the "f" core. Right now it&#39;s only that core that has it available. If you need one really bad you can always re-invent the wheel and make one (binary divider) since I&#39;m 99% sure that&#39;s what altera does and add it as a custom instruction.

Chances are in the next release it will be available for all cores since it&#39;s not DSP dependent anyway (so it should work on Cyclone or Stratix and all three cores).

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I don&#39;t know if Cyclone II would have it in the GUI but it shows up as a check box under the "f" core.[/b]

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This is true if I select a Stratix device in "Target Device Family". But for a Cyclone/CycloneII Devices the checkbox is hidden. At least for my SOPC-Builder 4.1 Build 207.

We decided to use a custom instruction for multiplication and division until this options is available in a future release. Is there any way to tell the compiler to use such an instruction instead the standart mul?

I don&#39;t think you can, I think you are stuck using the standard inst_name(A,http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif ; format.

Try editing the ptf file of the nios to see if you can get it working there (James a while back showed me how to disable the hardware multiplier in that file so maybe you&#39;ll be able to invoke it???? assumming that hardware implementation for that in cyclone is already present). <----- Really doubt it will work though.

If you generate for a Stratix device and then really compile it on Cyclone device,

you will get a hardware multiplier. However, note that since Cyclone has no DSP multiplier cells

like Stratix does, Quartus will construct the multiplier using LEs. This has the effect of

increasing the size of the Nios II core by 2X-3X and cutting the frequency by 2X-3X.

This is why it wasn&#39;t included as an option in Nios II release 1.0 since we did not

think it would be an attractive option for most customers.

Elan. Would multiplies and divides in about 35 clock cycles be good enought times for you? If so you could contruct these in hardware and use them as custom instructions (multiplication is a bunch of additions, and division is a bunch of comparisons and subtractions).

For both I&#39;m guessing you are looking at around 300-350LEs to implement those for the NIOS.

Hope that gives you some hope http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

As for the divide checkbox not being available under cyclone, I&#39;ll look into this.

I believe it is just a packaging choice that you only can get divide if you get multiply.

Since there is no multiply on cyclone, there is no divide.

However, I designed divide to be independent of multiply so it should work fine.

What&#39;s required is some PTF changes. How about you email your Nios II class.ptf and

your system.ptf and I&#39;ll see about making the changes? My email is jball@altera.com.

As for multiply, you could use a custom instruction but there is no way to get the compiler

to use it when you use the * operator. You&#39;ll have to change all your source code that

wants to use the fast multiply to call the multiply instruction instruction. There are macros

defined for you by SOPC Builder that will call a custom instruction from C-code or assembly.

Hi,

My 2c - if you want a multiply you can get one which runs at 85+Mhz, but takes 3-4 cycles, and a divide can run at speed, but takes multiple cycles. This allows NIOS to run all other stuff fast, but take more cycles to do mult and div - see my single precision FP stuff if you want - 3 cycles for add and 4 cycles for mult.

Oh yeah and if you want divide - I have one too (still refining for double precision atm)

Regards,

Steve.

I would be happy with a hw-multiply taking 3-4 cycles. For division 35 cycles are OK.

I don&#39;t see the point in Jame&#39;s post why a multi-cycle hw-multiplyer would cut frequency?

We will also take a look on Steve&#39;s FP-stuff.

Thanks

Chris