How to write a configurable SRAM controller for Avalon Tristate Bridge?

On my board, FLASH and SRAM share address bus and data bus. So I need a SRAM controller and FLASH controller for Avalon Tristate Bridge.

The Flash Memory Interface(CFI) IP in SOPC Builder 9.0 can support customized Data Bus width and Address Bus width. However, IDT71V416 SRAM controller in SOPC Builder 9.0 has a fixed DB width of 32, and this can not be modified.

Now I need DB&AB width configurable SRAM controller for Avalon Tristate Bridge. Can anyone give suggestion on how to write or obtain such a SRAM controller? Thanks.