How to vectorise many parallel input output ports into a single bus in Qsys or SOPC

Hi,

Instead of creating twelve Parallel input output ports (PIO) in Qsys/SOPC, is there any way I could vectorise many parallel input output ports (12 PIOs for example) into a single component in Qsys or SOPC?

Each PIO consists of 12 bits.

After creating the Nios system, I am going to include the Nios system block in the schematic in Quartus.

I need to feed the twelve PIOs into one single bus line in the schematic block in Quartus II. So I thought I want to combine the twelves PIOs so that in the NIos system block, it will only show one PIO instead of twelve.

I attached the image:

adc[1..12][11..0] is the 12 signals, each with 12 bits

in Nios system block, adc_v1_export is single signal, with 12 bits

I want to connect

What I have tried : I followed the advice in this link (http://www.alteraforum.com/forum/showthread.php?t=20876) but i got the following error (Error (275024): Width mismatch in port "adc_v1_export[11..0]" of instance "inst14" and type nios_system -- source is ""adc[0]""

).

Thank you