how to synthesize nios code by synplify ?

Synthesize or Compile (not sure if you mean HDL like verilog/VHDL, or you are talking about the actual software).

If you mean hardware synthesis I believe that symplicty has all the necessary features to do this easily so it should be documented somewhere (sorry I've only used that program to perform synthesis for another FPGA that didn't come with tools to do that).

I remember a while back reading that with NIOS I it was doable using that software using either some special feature or script, but again you should take a look at the documentation that the 3rd party provides.

Is there any particular reason for not using Quartus to do this task? Also are you trying to do this with NIOS I or II?