Altera_ForumHonored Contributor19 years agohow to slow down communication for LCD Dear all, i've hacked the driver of 16x2 to get 20x4 LCD display. It works, but the problem is, that I need to connect the display via quite long flat cable, which is of course not terminated,...Show More
Altera_ForumHonored Contributor19 years agoWhat about Slow Slew Rate option for LCD output signals interface? Did you try it?
Recent DiscussionsFPGA Community EnqueriesLPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 ProMultiple NIOS V ImplementationSolvednot able to use multiple niosV cores at the same timeNios V/m JTAG run‑control HALT fails — Debug Module healthy, hart never halts