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You don't need a fifo core....
The fifo core is only if you want to buffer avalon streaming data to avalon memory mapped data. I'm not sure how you are using the ADCs but my suspicion is that it is done through NIOS. Hence all you need to do is safe the sampled data into an array in C code (i.e. buffering in on-chip ram). The when you send out your uart information, you will be taking data out of that array.
In another one of your threads I posted a link to code that used uart interrupts. In that code, buffers are also used to store data for send out and collect incoming data. They were RxBuffer and TxBuffer. Look through that code, you should get an idea of how to use these buffer arrays.
If you want to use SDRAM, then you need to use IOWR and IORD functions to write your ADC data to specific SDRAM addresses, and then read the data out to send via uart. It's easier to use on-chip ram if you have the memory blocks.
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I dont know if this is feasible. What I am tempted to do, since the rate I can plot a graph is slower than the rate the incoming signal is read.
If I know the beginning of every incoming signal let say this point is indicated by a count=0, everytime I detect count=0, I know it is the beginning of each incoming signal, I keep track of how many cycles, let say, I only want to plot the graph every 10 cycles of the incoming signals, I plot cycle no.1, skip 10 cycles, plot cycle no. 11, skip cycle no.12 to 20, next plot cycle no. 21 etc ...in other words, it means I will lose some cycles in between which I am okay with this.
1. Do you think this method make any sense?
2. Do I still need buffering in this case?
3. How do I know how many cycles I need to skip? I assume it would depend on the incoming signal rate (50 Hz) and plot/receive rate (say 8 Hz), But I am not entirely clear about how to calculate...
The incoming signal (50 Hz) is from fpga vhdl, NIos system can read at 50 Mhz, but serial port receive rate or Matlab plot rate is 8 Hz.
Appreciate any input...thank you
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