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Honored Contributor
Honored ContributorHow to read signed values from FPGA in VHDL to Nios II system
Hi, I am reading a 14-bit signed value from a 14-bit vhdl port into a 16 bit signed variable in Nios II. There is no way for me to define it as 14 bits since the standard are alt_8, alt_16 a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- When using integer conversion one doesn't need to know the size difference when writing the code - it's more portable. Eventually one will forget why 'high+2 was used. Odds are the synthesis output is the same for both. --- Quote End --- But the OP is using the sfixed type, and this function exists exactly for this purpose. Using the to_integer function from sfixed directly will remove the fractional part, so you need to use appropriate type conversions. Your code also used the non-standard std_logic_arith library to convert the value.
