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Altera_Forum
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10 years ago

How to read signed values from FPGA in VHDL to Nios II system

Hi, I am reading a 14-bit signed value from a 14-bit vhdl port into a 16 bit signed variable in Nios II. There is no way for me to define it as 14 bits since the standard are alt_8, alt_16 a...
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Altera_Forum
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10 years ago

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Why not just sign extend?

output <= resize(a, a'high+2, a'low);

--- Quote End ---

When using integer conversion one doesn't need to know the size difference when writing the code - it's more portable.

Eventually one will forget why 'high+2 was used.

Odds are the synthesis output is the same for both.