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Honored ContributorHow to read signed values from FPGA in VHDL to Nios II system
Hi, I am reading a 14-bit signed value from a 14-bit vhdl port into a 16 bit signed variable in Nios II. There is no way for me to define it as 14 bits since the standard are alt_8, alt_16 a...
Altera_ForumHonored Contributor
Honored ContributorYou are aligning the data on the LSB. Don't do that - you want to align it on the sign bit.
For a 32-bit signed integer, bit-31 is the sign bit. For a 14-bit signed number, bit-13 is the sign bit: out <= in & "00" Alternatively, you can propagate the sign bit to all of the high bits: out <= (12 downto 0 => in(12 downto 0), others => in(13)) - or something like that.
