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Honored Contributor
Honored ContributorHow to read signed values from FPGA in VHDL to Nios II system
Hi, I am reading a 14-bit signed value from a 14-bit vhdl port into a 16 bit signed variable in Nios II. There is no way for me to define it as 14 bits since the standard are alt_8, alt_16 a...
Altera_ForumHonored Contributor
Honored ContributorAs the NIOS II is a microprocessor, the structure does not support any other than 8, 16, 32 Bits width.
Nevertheless... I'd suggest to rescale the 14Bit VHDL value to a 16Bit VHDL value prior reading it by the NIOSII by multiplying with "4" :-) Depending on the data representation this might be by a simple concatenate &"00" (for signed vector) or typing a "*4" to implement the multiplication. This also depends on the VHDL package you are using (which functions are defined and thus synthesizable)
