How to read a 24-bit signed signal from VHDL block fed in Nios II system - always +ve

--- Quote Start ---

Multiple ways,

alt_32 n;

// read the 24 bit signed signal

n = read_port;

// if the sign bit is set extend it to bit 31

if (n & 0x08000000)

n |= 0xf0000000;

Is the pio module your custom vhdl code or is it a qsys library module?

--- Quote End ---

Thanks kflynn for your reply... To answer your question, it is the standard qsys pio module.

If I understand correctly, guess it is typo from you? it should be as follow:

if (n & 0x00800000)
   n |= 0xff000000;

Please correct me if I am wrong, thank you!