How to read a 24-bit signed signal from VHDL block fed in Nios II system - always +ve

If I understand you correctly, you are reading a 24 bit signed value from a 24 bit port into a 32 bit signed variable then you have extend the most significant bit into bits 24 through 31.

1 represented with 24 bits is 0x000001, which when read as a 32 bit number is 0x00000001 which is the same.

-1 represented with 24 bits is 0xffffff, which when read as a 32 bit number if 0x00ffffff which is a positive value of 16777215.

When the msb is extended into bits 24 thru 31 you get 0xffffffff which is -1.