Honored Contributor
Honored Contributorhi all:
I use the opencore I2C control the encode 7113 success by fisher and slava help. Thank you. The following is my codes.I wish it can help othters. # define BIT0 0x01# define BIT1 0x02# define BIT2 0x04# define BIT3 0x08# define BIT4 0x10# define BIT5 0x20# define BIT6 0x40# define BIT7 0x80 // I2C REGISTERS# define I2C_PRERLO 0# define I2C_PRERHI 1# define I2C_CTR 2# define I2C_TXR 3# define I2C_RXR 3# define I2C_CR 4# define I2C_SR 4 # define CTR_EN BIT7# define CTR_IEN BIT6 # define CR_STA BIT7# define CR_STO BIT6# define CR_RD BIT5# define CR_WR BIT4# define CR_NACK BIT3 // # define CR_NC1 BIT2# define CR_NC2 BIT1# define CR_IACK BIT0 # define SR_RXNACK BIT7# define SR_BUSY BIT6# define SR_AL BIT5# define SR_NC1 BIT4# define SR_NC2 BIT3# define SR_NC3 BIT2# define SR_TIP BIT1# define SR_IF BIT0 # define I2C_WR 0# define I2C_RD BIT0 # define DELAY_TIME 5 //saa7113 macro-definition# define s_7113addr_w 0x4a# define s_7113addr_r 0x4b int i2cMaster_init(void) { IOWR(INCODE_I2C_MASTER_BASE,I2C_CTR,0x00); // disable i2c IOWR(INCODE_I2C_MASTER_BASE,I2C_PRERLO,99); // sclk = 100khz IOWR(INCODE_I2C_MASTER_BASE,I2C_PRERHI,0); // sclk = 100khz IOWR(INCODE_I2C_MASTER_BASE,I2C_CTR,CTR_EN); // enable i2c return 0; }; int encode7113_write_byte(unsigned char subaddr, unsigned char data) { if(encode7113_write_sl_waddr_subaddr(subaddr) == -1) { return -1; } if(encode7113_write_sl_data(data) == -1) { return -1; } return 0; } int encode7113_write_sl_waddr_subaddr(unsigned char subaddr) { // set start condition and write slave address IOWR(INCODE_I2C_MASTER_BASE,I2C_TXR,s_7113addr_w); IOWR(INCODE_I2C_MASTER_BASE,I2C_CR,CR_STA | CR_WR); if(waiting_for_tip() == -1) { return -1; } if(waiting_for_rxnack() == -1) { return -1; } //write subaddres IOWR(INCODE_I2C_MASTER_BASE,I2C_TXR,subaddr); IOWR(INCODE_I2C_MASTER_BASE,I2C_CR, CR_WR); if(waiting_for_tip() == -1) { return -1; } if(waiting_for_rxnack() == -1) { return -1; } return 0; } int encode7113_write_sl_data(unsigned char data) { IOWR(INCODE_I2C_MASTER_BASE,I2C_TXR,data); IOWR(INCODE_I2C_MASTER_BASE,I2C_CR, CR_STO | CR_WR); if(waiting_for_tip() == -1) { return -1; } if(waiting_for_rxnack() == -1) { return -1; } return 0; } int waiting_for_tip(void) { unsigned char cnt=20*DELAY_TIME; unsigned char status; status = IORD(INCODE_I2C_MASTER_BASE,I2C_SR); for(; cnt != 0; cnt--) { if(status & SR_TIP) { status =IORD(INCODE_I2C_MASTER_BASE,I2C_SR); } else { break; } if(cnt == 1) { printf("write slave address TIP fail\n"); return -1; } } return 0; } int waiting_for_rxnack(void) { unsigned char cnt=20*DELAY_TIME; unsigned char status; status = IORD(INCODE_I2C_MASTER_BASE,I2C_SR); for(; cnt != 0; cnt--) { if(status & SR_RXNACK) { status =IORD(INCODE_I2C_MASTER_BASE,I2C_SR); } else { break; } if(cnt == 1) { printf("RXNACK fail\n"); return -1; } } return 0; } unsigned char encode7113_read_byte(unsigned char subaddr) { unsigned char data; if(encode7113_write_sl_waddr_subaddr(subaddr) == -1) { return 0; } // set start condition and read slave address IOWR(INCODE_I2C_MASTER_BASE,I2C_TXR,s_7113addr_r); IOWR(INCODE_I2C_MASTER_BASE,I2C_CR,CR_STA | CR_WR); if(waiting_for_tip() == -1) { return 0; } if(waiting_for_rxnack() == -1) { return 0; } //set nack read and stop condition IOWR(INCODE_I2C_MASTER_BASE,I2C_CR, CR_RD | CR_NACK | CR_STO ); data = IORD(INCODE_I2C_MASTER_BASE,I2C_RXR); printf("data = %x\n",data); return data; }
