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Altera_Forum's avatar
Altera_Forum
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21 years ago

How to generate sof of FPGA when using ROM?

My design has embeded a ROM of 4096bytes inside FPGA. How could I modify the content of ROM in sof file without recompiling the whole design?
Altera_Forum's avatar
Altera_Forum
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21 years ago

No. Sorry.

The Quartus II assembler (the stage after routing) needs more information than is available in the SOF file - for example it needs to know which memories your ROM data is initialising etc.

Your other guy doesn't need to know VHDL, they just need to have Quartus installed and be able to check the VHDL out of your version control system and press the start button. Is there a reason why they can't use the "download and debug" flow which the IDE uses? It can usually write to SOPC builder created ROMs.