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Altera_Forum's avatar
Altera_Forum
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21 years ago

How to generate sof of FPGA when using ROM?

My design has embeded a ROM of 4096bytes inside FPGA. How could I modify the content of ROM in sof file without recompiling the whole design?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Quartus "smart compile" should help you.

This feature skips compilation stages which aren't needed - in this case it can skip synthesis and routing and just rerun the final stages of compilation.

You can turn it on from the Quartus Assignments/Settings menu - choose "Compilation tools settings" in the tree and then tick the box.

You may find that the "incremental compile" option is useful.