Forum Discussion
Altera_Forum
Honored Contributor
19 years agoit's been so long since I posted on this issue and since then I have had resolution. As it turned out the Altera provided CPLD "configuration controller" does not release the flash I/O pins to tri-state when it is done configuring the FPGA. This was the first problem and so I added TRI's to the outputs. But, I had forgotten to make pin assignments for a USB controller chip's control lines that are on the same avalon tri state bus. So, the Nios during flash programming was contending with the USB controller (who was supposed to be quiet on the bus).
Alas, the flash programmer has been working fine ever since then, but NOTE THAT THE VERIFY ALWAYS FAILS EVEN THOUGH DOING A READBACK OF FLASH PROVES THE FLASH CONTENTS ARE 100% CORRECT. No clue why the verify fails - we just ignore it.