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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to disable MAC-PHY communication ?

Hello, I am not sure why do we get "TSEMAC SW reset bit never cleared!" : We are connecting the FPGA to network switch, (unmanaged switch), so we removed all communication with phy , by disabling M...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello,

Yes, this might be the reason.

Kindly take a look at this document:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf#page=52

The software reset is 1 when the clocks are not available, either cable disconnected, or PHY disconnected. In your case, since there is no PHY, the soft reset is kept high.

The Nichestack application requires a phy to run. If you have the phy already in your system, I recommend to enable the MDIO and connect the phy to it. Then run the Nichestack application and see if you can pass the reset issue.

If you want to run the system without phy, then Nichestack will not help you. You need to develop your own application to run the loopback test.

Hope this might help.

Thank you.

  • rshal2's avatar
    rshal2
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi,

    Not sure I understand....

    The reset mac is not related to Nichestack . It is done in low level ( TSE registers).

    The issue is it not a limitation of Nichestack as you said, but of intel's TSE, Right ?

    When working with unmanaged switch (no cpu mode), there is no need to communiate with phy. We want it to run phyless.

    Therefore, the question is why TSE reset should fail without phy.

    Is there a way to overcome this limitation in TSE core ?

    Thanks