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first, how do you plan to control the dma engine? from the pci bus? --- Quote End --- Can I control the DMA in both way? Either from the PCI bus or from an user ip core in the inside of the FPGA? What do I need to do? In either way, how can I set the source/destination address and the interrupt to the DMA? If I want to control the DMA from inside, I shoul connect the User IP core to the DMA's "control slave port", is that right? <div class='quotetop'>QUOTE </div> --- Quote Start --- Second, I gather you want the board to master both PCI reads and Memory writes or are you just trying to access memory from the PCI bus?[/b] --- Quote End --- Yes I want to set the PCI as a master device, so is the memory controller. Thanks for your reply, Mike. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20677)</div> [/b] --- Quote End --- I do not believe the Avalon PCI core will allow the Avalon DMA core to generate a PCI interrupt? In any case, the PCI core is much more expensive than the NiosII core so complicating the design by trying to connect directly to the PCI alone is kind of asking for trouble. That being said... If you can get the DMA engine's IRQ to trigger a PCI interrupt then the design will require a PCI Core, a SDRAM (memory controller) Core, and the DMA controller Core all connected on the Avalon bus via SOPC Builder. Using the Altera DMA, PCI, and SDRAM core documentation should allow you to program up the DMA controller via the PCI bus since the PCI Core from Altera can be a Master / Slave device. Mike
