How to connect qsys clock output pin from PLL (C0 and C1) to two physical pin in MAX1

Yeah. That was the idea but I couldn't find a clean SDRAM example. The Altera web store shows a "Hello world" example with "off-chip memory" but it is mislabeled because it uses ocram instead. The one I'm using is the Nios full demo but it has a lot of stuff. I took my project that works and added the pll and sdram settings from the nios full demo. The problems is most of the demos and documents miss a few crucial steps and new me gets lost. It's a learning process, if it were too easy it would be boring :-). Thanks.