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Altera_Forum
Honored Contributor
Honored ContributorHow to connect qsys clock output pin from PLL (C0 and C1) to two physical pin in MAX1
Hi all, I'm new to fpga. I got a BeMicro MAX10 and I'm using qsys and the eclipse tool to make a nios2 system. I'm using quartus ii web v15.02. I got a system that works: nios2, ocram, leds,...
Altera_ForumHonored Contributor
Honored ContributorYes, a clock bridge is used to bring a PLL generated clock out.
Rather than trying to make a project based on an Altera project, I'd suggest taking a step back. Start with an SDRAM example project for your exact board. Verify the hardware by loading the already compiled output file. Once the hardware is known good, make sure you can build the project, without changes, from scratch. This will verify that you know how to build it. Make sure you can create working output files on your machine with the Quartus & eclipse versions you intend to use with the source files from the example. After doing all this, make small changes to the example, testing them one by one until it has what you need.
