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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to combine two Asynchronous SRAM chips

In my new design I need a lot of Asynchronous SRAM- at least 8 MBytes. A single chip SRAM or any DDRs are not acceptable (because of the high-temp requirements). The only way for me is to combine two asycnhronous SRAM chips of 4MBytes. I've tried to find a good example of such a circuitry, but all I found is a short example in the Quartus 4 manual. To combine two SRAM chips having 8-bit databus they suggest to share the address bus and to build data bus as 8+8=16 bit. Unfortunately the example has no details, just a diagram. I am looking for some application note or an example on how to handle this with SOPC builder.

Probably I will need to build a custom component (like they did it for SRAM in DE1 Nios tutorial), but I am not sure what to do with the numerous pins like nBYTE, CE1, CE2,etc.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Use Altera Tri-state bridge in SOPC and connect both chips address pins in parallel. Use data pins and all other control pins separately. When You add both chips to the same tri-state bridge in SOPC, go again to the bridge properties and set the address pins to be shared.

    You can also connect both chips separate at all, then You'll need two tri-state bridges without any pin sharing.