Honored Contributor
Honored Contributori am implentming a nios 2 sopc developing board based on altera's ep2c35f672 device.
there are two schemes,
1,sram+nios2+nios2, the nios2s share the same program memory.
2,sram+nios2 + sram+nios2, the nios2s use respective memory.
i am not clear if the 2nd scheme will be much faster than the 1st.
so will you please give me some hints?
will the 2nd improve my board's speed greatly?
and how about sdram? how to get rid of the bottle-neck?
(assuming that the nios2s run at 100mhz,the delays of sram is 10 ns.)
thank in advance!
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--- Quote End --- The question is not simple... and, as usual, the answer is: - it depends - :-) - The second solution will reduce the conflicts of the two Nios CPUs while accessing the shared bus, in general it should be more performant. - Having cache memory on each Nios II can mitigate the effect of the conflicts on the shared bus (again, that depends on the application. In some applications, caches does not help a lot). - The structure of the application (the pattern of accessing multicore shared data) can influence a lot the conflicts on the shared bus. Note also these accesses have to be carried out with cache disabling techniques. A good sw partitioning among the CPUs in this case is needed to avoid too many conflicts. Just a curiosity, what kind of application are you working on? Paolo
