Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

How to change the cpu working frequency of uclinux?

In SOPCBuilder, there's a choice of the clock frequency for NIOSII Processor component.

And in the uclinux, I believe there are also alternate option locates in the .c file.

I don't know how to change the cpu working frequency of uclinux?

cat /proc/cpuinfo there's only half of the highest freq of cpu.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Do you want to dynamically change the CPU frequency ?

    That is an interesting issue. (Especially for implementing a power saving mode.)

    I don't suppose this is provided by the NIOS SOPC module. But I suppose the clock for the CPU can be taken from any source within the FPGA and thus you should be able to implement some hardware for a variable clock source module using HDL code (e.g. changing the divide factor of a PLL) . Same could be an Avalon bus slave.

    Now you would need to do a kernel driver that writes to the clock hardware and as Linux does have a Power management subsystem, if done correctly same could access your Kernel driver to do the standard (e.g. Laptop-like) clock frequency handling for power saving

    On the long run I do plan for something like this, too.

    -Michael
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    <div class='quotetop'>QUOTE (mschnell @ Aug 14 2009, 03:05 AM) <{post_snapback}> (index.php?act=findpost&pid=23508)</div>

    --- Quote Start ---

    Do you want to dynamically change the CPU frequency ?

    That is an interesting issue. (Especially for implementing a power saving mode.)

    I don&#39;t suppose this is provided by the NIOS SOPC module. But I suppose the clock for the CPU can be taken from any source within the FPGA and thus you should be able to implement some hardware for a variable clock source module using HDL code (e.g. changing the divide factor of a PLL) . Same could be an Avalon bus slave.

    Now you would need to do a kernel driver that writes to the clock hardware and as Linux does have a Power management subsystem, if done correctly same could access your Kernel driver to do the standard (e.g. Laptop-like) clock frequency handling for power saving

    On the long run I do plan for something like this, too.

    -Michael[/b]

    --- Quote End ---

    I believe it&#39;s a very interesting process to change the frequency,too. I will gather more knowledge in the following semester, and enjoy the next amazing semester in my life.