Forum Discussion
Altera_Forum
Honored Contributor
16 years agoDo you want to dynamically change the CPU frequency ?
That is an interesting issue. (Especially for implementing a power saving mode.) I don't suppose this is provided by the NIOS SOPC module. But I suppose the clock for the CPU can be taken from any source within the FPGA and thus you should be able to implement some hardware for a variable clock source module using HDL code (e.g. changing the divide factor of a PLL) . Same could be an Avalon bus slave. Now you would need to do a kernel driver that writes to the clock hardware and as Linux does have a Power management subsystem, if done correctly same could access your Kernel driver to do the standard (e.g. Laptop-like) clock frequency handling for power saving On the long run I do plan for something like this, too. -Michael