My thinking is most peripherals contain one or more registers (addresses) that you write to change the hardware and read to get the result. We have an internet checksum hardware module in SOPC. We write the base address to checksum to a register and the size in bytes to another register. That second write kicks off the hardware loop to read and checksum. A register is read until the hardware is done - the hardware sets a "done" bit. Then we read a second register which contains the internet checksum.
Our HAL for this was imply an H file with the function:
u16 CalcInternetChecksum(u8 *buffer, u32 length);
And we use a C function that writes and reads the registers per the above description. We simply used IOWR and IORD to the# define of the BASE address in System.h (which is the peripheral name). System.h has something like:
# define INTERNET_CHECKSUM_0_BASE 0x04001000
And our H file also has# defines which are custom register offsets from the base address of the peripheral.
# define CHECKSUM_ADDR 0 // start addr# define CHECKSUM_LEN 1 // length# define CHECKSUM_DONE 2 // non-0 when done, 0 otherwise# define CHECKSUM_RESULT 3 // checksum result
Our hardware designer defined in his Verilog code these offsets (which are 32-bit registers).
For example, this is an example checksum function:
u16 CalcInternetChecksum(u8 *buffer, u32 length)
{
IOWR(INTERNET_CHECKSUM_0_BASE, CHECKSUM_ADDR, (u32) buffer);
IOWR(INTERNET_CHECKSUM_0_BASE, CHECKSUM_LEN, length);
while(IORD(INTERNET_CHECKSUM_0_BASE, CHECKSUM_DONE)==0)
; // Loop til done
return IORD(INTERNET_CHECKSUM_0_BASE, CHECKSUM_RESULT);
}
If the base address changes in SOPC, this code will adjust to that. If the designer were to change the register offsets in the Verilog, then *I* would have to update the H file that contains those# defines.
The only thing SOPC did for me was to export the base address into System.h. That's all I need from it to write the rest of this simple HAL.
I hope this example is helpful!
Bill
Honored Contributor
