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I think a close example would be computing a SHA512/MD5/etc hash for a given input.
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For an application where there is a large volume of data, having a NIOS processor perform calculations on the data would result in pretty poor performance. What you want is a streaming data processing system, where the NIOS processor is used for control.
There is an example somewhere on the Altera web site showing a checksum accelerator. This looks like it might be it:
http://www.altera.com/support/examples/nios2/exm-checksum-acc.html You will want something similar to this for the processing part of your design. The next thing you need to analyze is; what is the I/O bandwidth you require to get data on and off the FPGA? I suspect a PCIe based board might be your best bet. You can determine the maximum bandwidth to the PCIe board, and then determine whether a Cyclone device or a Stratix device is needed for processing that bandwidth. If that bandwidth is below what you were hoping for, then that tells you how many boards you will need, or whether you need to consider a higher bandwidth interface (eg., more PCIe lanes per PCIe board).
Cheers,
Dave
Honored Contributor
