how does the cyclone dev board boot from flash?

The MAX controller is used to clock FPGA configuration data into the cyclone device from CFI (AMD) flash on the board; Cyclone cannot configure itself from CFI flash alone.

The EPCS (serial) flash devices can be used with the FPGA, and in that case, no MAX chip is necessary, as the Cyclone device has dedicated configuration logic to configure itself from EPCS chips.

Note that FPGA configuration is separate from Nios II software -- I am refering to the operation that loads the design into the FPGA at power-up.