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Honored Contributor
Honored ContributorHow does NiosII communicate with other FPGA blocks
Hi, I am designing a simple CPU+FPGA application. The FPGA has data bus for setting registers, one at a time. The data bus includes inputs: TSData[15:0] Addr [3...
Altera_ForumHonored Contributor
Honored ContributorUse component editor (PIO is too simple for most external interfacing). If your interface uses non-Avalon timing add some extra logic to conform to the standard (see the Avalon Bus Spec). If your interface goes off chip and runs at a significantly high speed I recommend re-syncronizing the signals with registers.
