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Honored Contributor
Honored ContributorHow does NiosII communicate with other FPGA blocks
Hi, I am designing a simple CPU+FPGA application. The FPGA has data bus for setting registers, one at a time. The data bus includes inputs: TSData[15:0] Addr [3...
Altera_ForumHonored Contributor
Honored ContributorHi,
I think you can use user interface logic. You can write the proper timing logic between avalon and user interface and add to the SOPC.
