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Altera_Forum's avatar
Altera_Forum
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20 years ago

How consolidate RBF-file with program for NIOS

Hello

It is my first post on this forum, so sorry if I select wrong place.

I have problem with auto-boot on Stratix.

I build project in Quartus and result of this work is RBF file. But when I load this (rbf) to FPGA, program doesn’t work. I must always on start use NIOS IDE and load program (compiled form C) from this aplication, for it I use JTAG.

So, my question is how add program for nios to RBF-file? I load RBF-file to FPGA by my own application (Stratix is on Tsunami PC104 board was connected to PC by PCI bus).

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi gkarpiel,

    > So, my question is how add program for nios to RBF-file?

    Does your program run from an on-chip RAM/ROM? Or do you have external

    memory?

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    My program is running from on-chip MEMORY ROM/RAM,

    so Is it possible?
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi gkarpiel,

    > My program is running from on-chip MEMORY ROM/RAM,

    > so Is it possible?

    Yes. On chip memory components are initialized from the contents of a .hex file.

    For example, if you have an on chip rom component named "irom", Quartus

    will look for a file named "irom.hex" by default -- you can look in your ptf file

    to see the name. You can use elf2hex to generate the file ... although I believe the

    IDE can do it automatically for you (I always do these tasks via command line).

    Regards,

    --Scott
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi

    I have on-chip memory, so file "onchip_memory_0.hex" was generated automatic by NIOS IDE (ok, it's true). Next, I set “start compilation” and now I have sof-file and rbf-file with program for NIOS (you have right to). And now, I have second problem, when I load sof –file (JTAG) or RBF-file (my application) to FPGA, program doesn’t start, but when I load by NIOS IDE program works ok. I don’t know what NIOS IDE change in FPGA, because if I load sof (JTAG) or rbf (my application) AGAIN (after NIOS IDE), all works ok. Now, I can load different programs with different structures FPGA (different mode in blinking LED) and all works fine. So, what I should do to force auto-start program after power on?

    Maybe, I must set some RESET signals or something?
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi gkarpiel,

    > So, what I should do to force auto-start program after power on?

    Sounds like a hardware issue. You should probably review the schematic and the

    board's hardware manual to see how reset is handled.

    Regards,

    --Scott