Forum Discussion
Altera_Forum
Honored Contributor
20 years agoHi
I have on-chip memory, so file "onchip_memory_0.hex" was generated automatic by NIOS IDE (ok, it's true). Next, I set “start compilation” and now I have sof-file and rbf-file with program for NIOS (you have right to). And now, I have second problem, when I load sof –file (JTAG) or RBF-file (my application) to FPGA, program doesn’t start, but when I load by NIOS IDE program works ok. I don’t know what NIOS IDE change in FPGA, because if I load sof (JTAG) or rbf (my application) AGAIN (after NIOS IDE), all works ok. Now, I can load different programs with different structures FPGA (different mode in blinking LED) and all works fine. So, what I should do to force auto-start program after power on? Maybe, I must set some RESET signals or something?