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Altera_Forum
Honored Contributor
Honored Contributorhow can i access the output
my custom logic takes 26 clk cycles to produce the output, how can i access the output just it finish processing the inputs.
Altera_ForumHonored Contributor
Honored Contributorbut my logic is pipelined, and have an input each clk, is ther any function that can use as a timer in c, instead implementing it in vhdl.
