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Honored Contributor
Honored Contributorhelp on SDRAM
Hello. I have a big problem with my board. My board has a EP1CQ240C6, one flash Intel E28F128, one SDRAM MT48LC4M32, one EPCS4 and a LAN91C111. The CPu clock is 50 MHz. I have made a...
Altera_ForumHonored Contributor
Honored ContributorIn general, u can design a phase shift using a faster clock to re-sample your clock. But having a 50 MHz clock u have 20 ns period, so if u generate a slower clock, u have a maximum resolution shift of 10 ns and u can't realize the 3.5 ns shift.So it's a problem...
Can u reconfigure your I/O pins to use PLL? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
