help on SDRAM

Hi sol,

I think that your problem is not the frequency of the clock to SDRAM but the phase shift between this clock and the processor clock: u must set a phase shift between these clocks, we used 3.5 ns in a EP1C20 board. I think u could realize it in VHDL...

Hi Soin£¬ thank u for your answer http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

Maybe the phase shit is the problem, but how can I generate a phase shift without PLL.

For example , the main clock is 50MHz, if I want to get the 3.5ns, the phase shift is approximate 65 degrees.

In the file "sdram.vhd", I didn&#39;t see the content about the phase shift.

sol *_*

In general, u can design a phase shift using a faster clock to re-sample your clock. But having a 50 MHz clock u have 20 ns period, so if u generate a slower clock, u have a maximum resolution shift of 10 ns and u can&#39;t realize the 3.5 ns shift.So it&#39;s a problem...

Can u reconfigure your I/O pins to use PLL? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Hi Soin, I am back.

Maybe I can try it.

"This PLL introduces a phase-shift which compensates for board-level delays in the clock network. Other boards may require different settings."

Why need a compensate for board-level delays? And how to calculate the delays of my board?

I am beginner ......

Thank u http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Hi sol,

While not SDRAM-specific, there is a document in Nios II 5.0 which may help you understand how to calculate phase-shift values and determine how fast you can run SDRAM without using a PLL for phase-shifting. The document describes the new SSRAM interface in Nios II 5.0 and is "ssram_interface_readme.html" in the Nios II installation&#39;s &#39;documents&#39; folder.

You should study carefully the first section that describes the memory interface with no phase shift -- it will show you how to calculate the maximum speed which you can run with no phase shift. You will need:

1. To obtain the data sheet for your SDRAM and examine timing parameters (Tsu, Tco for all inputs, worst-case)

2. Look at the quartus timing analysis report for Tco and Tsu times for all pins to and from SDRAM

3. Perform timing analysis to see what f-max you can run at with no phase shift

Important note: Even without a PLL there will be a phase-relationship between FPGA (Avalon) clock and the clock you drive from the FPGA to SDRAM. You should be able to find this delay in the Quartus Tco report.

Good luck!